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16TE3 Mezzanine

Data sheet / Specifications

Drivers and Software
Documentation

Multiple T3 or E3 Interfaces Mezzanine Board

Features

  • 16 E3/T3 full duplex interfaces
  • User-programmable FPGA up to Xilinx XCV2000E (PCI SS) or XC2VP70 (PCI GS)
  • Local memory up to 1 gigabyte (PCI GS) 16 independent DMA channels to host memory Fast transfers using a 66 MHz 32-bit PCI

Description

    The 16TE3 is a mezzanine board for the PCI SS, PCI GS, or PCIe8 LX main board, and has 16 T3 or E3 tellecomunication interfaces that can be used for complex, user-defined telecommunications applications. A large Xilinx Virtex (TM)-E (PCI SS) or Virtex-II Pro (PCI GS) FPGA and associated memory allows the user to process a large amount of tellecomunications serial. The high-speed 16-channel DMA controller allows flexible access to host memory.

Applications

  • Monitoring serial data communications
  • Generating T3- or E3-compatible signals

System Requirements

    Computer with Intel, AMD or SPARC processor, 512 KB memory, AGP or other non-PCI video, 66Mhz or faster PCI bus when used with the PCI SS/GS main board, or 8-Lane PCI Express when used with the PCIe8 LX. Will work in a 33Mhz PCI slot but max data throughput will be limited to ~90 MB/sec pixel data [more about bandwidth requirements].

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Engineering Design Team
1100 NW Compton Dr, Suite 306
Beaverton, OR 97006