3P Mezzanine

3P is a three-port mezzanine board that pairs with a PCI Express main board to provide three independent channels, each supporting an optional SFP or SFP+. Channel 0 supports up to 10GbE (optical), while channels 1 and 2 each support 1GbE (electrical or optical) or OC3/12/48 (STM1/4/16).

The user-configurable FPGA (Xilinx Virtex 6 XC6VLX240T, LX365T, or SX315T) can access three independent 512 MB blocks of DDR2 DRAM, which can be used as data buffers. Two of these can be combined to create a memory block of 1GB.

Each channel links to a SERDES via a specialized LIU or, optionally, via a multi-gigabit transceiver (MGT) in the FPGA. For channel 0, the LIU is 10G; for channels 1 and 2, it is SONET/ SDH. Each channel has its own reference clock, programmable from 10 to 210 MHz. A time code input (1 pps or IRIG‑B) also is included.

EDT provides FPGA configuration files to support the following: 1GbE and 10GbE data at the PHY layer (raw, framed, and framed and descrambled); SONET / SDH (raw, framed, framed and descrambled, header, and payload data); and demultiplexing to VC-4C payloads. Custom configuration files can be requested.

The main board supplies DMA, plus additional memory and programmable FPGA resources.

For details on system requirements and EDT-provided software driver packages, see specifications for the PCIe8 LX main board.