For instance, the FIFO stores information processed by the user interface Xilinx until the PCI Xilinx retrieves it across the PCI bus. The PCI bus normally sends information in bursts, so the FIFO allows this same information to be sent smoothly. When acquiring or sending data, flush the FIFO immediately before performing DMA. This also resets the FIFO to an empty state. The following subroutines either flush the FIFO or set it to flush automatically at the start of DMA.
Functions | |
| void | edt_flush_fifo (EdtDev *edt_p) |
| Flushes the board's input and output FIFOs, to allow new data transfers to start from a known state. | |
| int | edt_get_firstflush (EdtDev *edt_p) |
| OBSOLETE. | |
| int | edt_set_firstflush (EdtDev *edt_p, int val) |
| Tells whether and when to flush the FIFOs before DMA transfer. | |
| void edt_flush_fifo | ( | EdtDev * | edt_p | ) |
Flushes the board's input and output FIFOs, to allow new data transfers to start from a known state.
| edt_p | pointer to edt device structure returned by edt_open or edt_open_channel |
| int edt_get_firstflush | ( | EdtDev * | edt_p | ) |
OBSOLETE.
Returns the value set by edt_set_firstflush(). This is an obsolete function that was only used as a kludge to detect EDT_ACT_KBS (also obsolete).
| edt_p | pointer to edt device structure returned by edt_open or edt_open_channel |
int application_should_already_know_this; application_should_already_know_this=edt_get_firstflush(edt_p);
| int edt_set_firstflush | ( | EdtDev * | edt_p, | |
| int | flag | |||
| ) |
Tells whether and when to flush the FIFOs before DMA transfer.
By default, the FIFOs are not flushed. However, certain applications may require flushing before a given DMA transfer, or before each transfer.
| edt_p | pointer to edt device structure returned by edt_open or edt_open_channel | |
| flag | Tells whether and when to flush the FIFOs. Valid values are:
|
1.5.1