lib_ocm.c

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/* #pragma ident "@(#)lib_ocm.c 1.22 09/13/07 EDT" */

#include "edtinc.h"

#include "edt_bitload.h"

#ifdef _NT_
#else

#define __USE_GNU
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>

#include <stdio.h>

#include <stdlib.h>

#define HANDLE int


#endif

#include "edt_ocm.h"

/***************************************
* Some utility functions
* These probably ought to go in a general
* library file
**************************************/

#if 1

int
edt_reg_set_bitmask(EdtDev *edt_p, u_int reg, u_int mask, int state)

{

    return  (state)? edt_reg_or(edt_p, reg, mask) : edt_reg_and(edt_p, reg, ~mask);
}

#else

#define edt_reg_set_bitmask(edt_p, reg, mask, state) \
    ((state)? edt_reg_or(edt_p, reg, mask) : edt_reg_and(edt_p, reg, ~mask))

#endif


int
edt_wait_register_bits_low(EdtDev *edt_p, u_int reg, u_int mask, int timeout)

{
    int t = 0;

    while ((t < timeout || !timeout) && (edt_reg_read(edt_p,reg) & mask))
    {
        edt_msleep(100);
        t += 100;
    }

    return (t > timeout && (timeout != 0));
}


int
edt_wait_register_bits_high(EdtDev *edt_p, u_int reg, u_int mask, int timeout)

{
    int t = 0;

    while ((t < timeout || !timeout) && 
        !((edt_reg_read(edt_p,reg) & mask)==mask))
    {
        edt_msleep(100);
        t += 100;
    }

    return (t > timeout && (timeout != 0));

}

/**********************************
* These functions work the same 
* on both OCM and OC192
**********************************/

void
edt_ocx_enable_framing_errors(EdtDev *edt_p, int state)

{

    u_int mezzanine_offset = 0;

    if (edt_p->channel_no & 1)
    {
        mezzanine_offset = OFFSET_CH1_MEZ;
    }

    edt_reg_set_bitmask(edt_p, OCM_CH0_CNT_CTRL + mezzanine_offset,
        OCM_EN_ERROR_COUNT, state);

}


int 
edt_ocx_get_framing_errors(EdtDev *edt_p, EdtOCXFrameErrors *err_p)

{
    u_int mezzanine_offset = 0;

    if (edt_p->channel_no & 1)
    {
        mezzanine_offset = OFFSET_CH1_MEZ;
    }
    /* Assume frame counts are enabled */

    edt_reg_set_bitmask(edt_p, OCM_CH0_CNT_CTRL + mezzanine_offset , 
        OCM_ERROR_COUNT_HOLD, 1);

    err_p->b1_errors = edt_reg_read(edt_p, 
        OCM_CH0_B1_ERROR_CNT + mezzanine_offset);
    err_p->b1_error_mask = (u_char) edt_reg_read(edt_p, 
        OCM_CH0_B1_ERROR_MASK + mezzanine_offset);
    err_p->b2_errors = edt_reg_read(edt_p, 
        OCM_CH0_B2_ERROR_CNT + mezzanine_offset);
    err_p->m1_errors = edt_reg_read(edt_p, 
        OCM_CH0_M1_ERROR_CNT + mezzanine_offset);
    err_p->lof_errors = edt_reg_read(edt_p, 
        OCM_CH0_LOF_CNT + mezzanine_offset);
    err_p->frame_pattern_errors = edt_reg_read(edt_p, 
        OCM_CH0_FRM_PAT_CNT + mezzanine_offset);
    err_p->false_frame_errors = edt_reg_read(edt_p, 
        OCM_CH0_FALSE_FRM_CNT + mezzanine_offset);

    edt_reg_set_bitmask(edt_p, OCM_CH0_CNT_CTRL + mezzanine_offset , 
        OCM_ERROR_COUNT_HOLD, 0);

    return 0;
}


int
edt_ocx_lock_local_clock(EdtDev *edt_p, int timeout)

{

    FENTER("edt_ocx_lock_clocks");

    if (edt_wait_register_bits_high(edt_p, PCD_STAT, LOCAL_SYS_LOCK,timeout))
    {
        edt_msg(EDTLIB_MSG_FATAL,"\rBaseboard System clock not locked");
        return -1;
    }

    edt_msg(EDTLIB_MSG_INFO_1,"Local System clocks locked \n");

    return 0;

}

int
edt_ocx_lock_channel_clock(EdtDev *edt_p, int channel, int timeout)

{
    int base_offset;

    FENTER("edt_ocx_lock_clocks");

    base_offset = (channel & 1) ? OFFSET_CH1_BASE:0;

    if (edt_wait_register_bits_high (edt_p, OCM_CH0_ENABLE + base_offset, SYS_LOCK,timeout))
    {
        edt_msg(EDTLIB_MSG_FATAL,"\rMezzanine System clock not locked");
        return -1;

    }

    return 0;

}

int
edt_msdv_load_default_mezzanine(EdtDev *edt_p, char *mezz_0)

{
    int rc = 0;

    char *bitname = "dvb_asi.bit";

    if (mezz_0)
        if (mezz_0[0])
            bitname = mezz_0;

    rc = edt_bitload(edt_p, ".", bitname, BITLOAD_FLAGS_MEZZANINE, 0);

    return rc;
}

int
edt_net10g_load_default_mezzanine(EdtDev *edt_p, char *mezz_0, char *mezz_1)

{
    int rc = 0;

    char *bitname = "net10g_5v_sdh.bit";

    FENTER("edt_net10g_load_default_mezzanine");
    if (mezz_0)
        if (mezz_0[0])
            bitname = mezz_0;

    rc = edt_bitload(edt_p, ".", bitname, BITLOAD_FLAGS_MEZZANINE, 0);

    if (rc == 0)
    {
        bitname = "net10g_s3_cfg.bit";

        if (mezz_1)
            if (mezz_1[0])
                bitname = mezz_1;

        rc = edt_bitload(edt_p, ".", bitname, BITLOAD_FLAGS_MEZZANINE | BITLOAD_FLAGS_CH1, 0);
    }

    return rc;
}

/***************************************
*
* OCM specific functions
* Most have equivalent OC192 functions
*
**************************************/

int
edt_ocm_lock_clocks(EdtDev *edt_p, int timeout)

{

    if (edt_ocx_lock_local_clock(edt_p, timeout) ||
        edt_ocx_lock_channel_clock(edt_p, 0, timeout) ||
        edt_ocx_lock_channel_clock(edt_p, 1, timeout))

        return -1;

    edt_msg(EDTLIB_MSG_INFO_1,"All System clocks locked          \n");

    return 0;

}


char *
edt_ocm_mezz_filename(EdtDev *edt_p, EdtLineRate line_rate)

{

    char *target_bitfile;

    switch (line_rate) {
        case OC3_RATE:      
        case OC12_RATE:     
        case STM1_RATE:
        case STM4_RATE:
            target_bitfile="ocm12.bit";
            break;

        case STM16_RATE:            
        case OC48_RATE:     
            target_bitfile="ocm48.bit";
            break;

        case GIGE_RATE:
            target_bitfile="ethernet.bit";
            break;
        
        default:
                target_bitfile = NULL;

    }

    return target_bitfile;
}

int
edt_ocm_load_default_mezzanine(EdtDev *edt_p, 
                               EdtLineRate line_rate,
                               char *mezz_0,
                               char *mezz_1)

{

    int rc = 0;
    int flags  = BITLOAD_FLAGS_OVR | BITLOAD_FLAGS_OCM;
    int rate = OC48_RATE;

    char *bitname;

    if (edt_p->channel_no == 0)
        rate = (line_rate)?line_rate:OC48_RATE;

    if (mezz_0 && mezz_0[0])
        bitname = mezz_0;
    else
        bitname = edt_ocm_mezz_filename(edt_p, rate);

    rc = edt_bitload(edt_p, ".", bitname, flags, 0);

    if (rc == 0)
    {
        flags |= BITLOAD_FLAGS_CH1;

        if (mezz_1 && mezz_1[0])
            bitname = mezz_1;
        else
            bitname = edt_ocm_mezz_filename(edt_p, OC12_RATE);

        rc = edt_bitload(edt_p, ".", bitname, flags, 0);

    }

    return rc;

}

int
edt_ocm_speed_capable(EdtDev *edt_p, EdtLineRate line_rate)

{
    int rc = -1;
    switch (line_rate) {
        case STM1_RATE:
        case STM4_RATE:
        case OC3_RATE:      
        case OC12_RATE:     
        case GIGE_RATE:
            rc =  0;
            break;

        case STM16_RATE:            
        case OC48_RATE:     
            if ((edt_p->channel_no & 1) == 0)
                rc = 0;
            break;

        case STM64_RATE:
        case OC192_RATE:
            rc =  -1;
            break;

        default:
            edt_msg(EDTLIB_MSG_FATAL,"Unknown bit rate %d\n", line_rate);
            rc =  -1;

    } 
    return rc;
}



int
edt_ocm_has_mezz_bitfile(EdtDev *edt_p, char *bitfile_name)

{
    int channel = edt_p->channel_no & 1;
    char *ch_id;
    int rc;

    FENTER_S("edt_ocm_has_correct_bitfile",bitfile_name);

    if (channel == 0)
    {
        ch_id  = edt_p->bfd.mezz_name0;
    }
    else
    {
        ch_id  = edt_p->bfd.mezz_name1;
    }

    /* check correct bitfile for channel 0 */
    rc = strncmp(ch_id, bitfile_name, strlen(bitfile_name));

    FRETURN_I("edt_ocm_has_correct_bitfile",rc);

    return rc;

}
int
edt_ocm_set_clock_select(EdtDev *edt_p, EdtLineRate line_rate)

{
    int channel = edt_p->channel_no & 1;
    int clk_select = CLK_SONET_SDH;
    int clk_val = OC3_STM1;
    int base_offset = 0;
    int mezzanine_offset = 0;
    int read_byte;


    FENTER_I("edt_ocm_set_clock_select", line_rate);

    switch (line_rate)
    {
    case OC3_RATE:          
    case STM1_RATE:
        clk_val = OC3_STM1;
        break;

    case OC12_RATE:      
    case STM4_RATE:
        clk_val = OC12_STM4;
        break;

    case STM16_RATE:        
    case OC48_RATE:         
        clk_val = OC48_STM16;
        break;

    case GIGE_RATE:
        clk_val = OC24;
        clk_select = CLK_GE | 0x4;
        break;

    }

    if (channel == 1) 
    {
        base_offset = OFFSET_CH1_BASE;
        mezzanine_offset = OFFSET_CH1_MEZ;
    }

    /* select the oscillator frequency */
    read_byte = edt_reg_read(edt_p, OCM_TX_CONFIG + mezzanine_offset); 
    read_byte &= ~CLOCK_SEL_MSK;
    read_byte |= clk_select;
    edt_reg_write(edt_p, OCM_TX_CONFIG + mezzanine_offset, read_byte );
    /* set LIU to correct multiplier */
    read_byte = edt_reg_read(edt_p, OCM_CH0_CONFIG0 + base_offset);  
    read_byte &= ~RX_SEL_MSK;
    read_byte |= clk_val;
    edt_reg_write(edt_p, OCM_CH0_CONFIG0 + base_offset , read_byte);  


    FRETURN("edt_ocm_set_clock_select");

    return 0;

}

int
edt_ocm_channel_lock_frontend(EdtDev *edt_p, EdtOCConfig *cfg)

{
    int done = 0;
    /* it takes 200 ms every time through */

    int timeout = cfg->timeout;
    int timer = 0;
    int timed_out = 0;

    uint_t base_offset = 0;
    uint_t mezzanine_offset = 0;
    int channel = edt_p->channel_no & 1;
    int rc;

    if (channel == 1)
    {
        base_offset = OFFSET_CH1_BASE;
        mezzanine_offset = OFFSET_CH1_MEZ;

    }
    /* Reset front end DPLLs */
    edt_reg_and(edt_p, OCM_CH0_ENABLE + base_offset,  ~(SLK_EN | PLL_EN));

    edt_reg_or(edt_p, OCM_CH0_ENABLE + base_offset, RAM_EN | SYS_EN);

    while (done == 0 && !timed_out)
    {

        /* check signal detect */
        if ((cfg->flags & EDT_OCX_NO_SIG_DET) ||
        edt_ocx_channel_signal_detect(edt_p))
        {
            /* enable SLK */
            edt_reg_or(edt_p, OCM_CH0_ENABLE + base_offset, SLK_EN); 
            edt_msleep(100); /* wait for the DCM to lock */
            timer += 100;
            /* test if SLK is locked */
            /* LOL is a reliable indication of some lock problems but not all */
            if ((edt_reg_read(edt_p, OCM_CH0_STATUS + base_offset) & LOL) == 0)
            {
                edt_reg_or(edt_p, OCM_CH0_ENABLE + base_offset, PLL_EN); 
                edt_msleep(100); /* wait for the DCM to lock */
                timer += 100;
                if ((done = (edt_reg_read(edt_p, OCM_CH0_ENABLE + base_offset) & RX_LOCK)) == 0)
                {
                    edt_msg(EDT_MSG_WARNING,"\rChannel %d FPGA PLL not locked check signal input type", channel);
                    /* reset slk and dcm enable */
                    edt_reg_and(edt_p, OCM_CH0_ENABLE + base_offset, ~(SLK_EN | PLL_EN));
                }
            }
            else
            {
                edt_msg(EDT_MSG_WARNING,"\rChannel %d LIU PLL not locked check signal input type", channel);
                /* reset slk and dcm enable */
                edt_reg_and(edt_p, OCM_CH0_ENABLE + base_offset, ~(SLK_EN | PLL_EN));
            }
        }
        else
        {
            edt_msg(EDT_MSG_WARNING,"\rChannel %d no signal detected -  check signal input", channel);
            edt_reg_and(edt_p, OCM_CH0_ENABLE + base_offset, ~(SLK_EN | PLL_EN));
            /* always imcrement timer at least one */
            timer ++;
        }  

        if (timeout)
            timed_out = timer >= timeout;

    }

    edt_msg(EDT_MSG_INFO_1,"\rChannel %d PLL locked                    \n", channel);

    /* make error negative */
    rc = -timed_out;

    return rc;

}
int
edt_ocm_channel_setup(EdtDev *edt_p, EdtOCConfig *cfg)


{
    int channel = edt_p->channel_no;
    int base_offset = 0;
    int mezzanine_offset = 0;
    u_char rx_ctrl ;
    u_char rx_filter ;

    FENTER("edt_ocm_channel_setup");

    if (edt_p->mezz.id == MEZZ_OC192)
    {
        edt_reg_write(edt_p, OC192_CHAN_SELECT, 0);     
    }


    if (channel == 1)
    {
        base_offset = OFFSET_CH1_BASE;
        mezzanine_offset = OFFSET_CH1_MEZ;

    }

    /* set local loopback if requested */
    edt_reg_set_bitmask(edt_p, OCM_CH0_CONFIG0 + base_offset, LOCAL_LOOP, (cfg->flags & EDT_OCX_LOOPBACK));

    /* set remote loopback if requested */
    edt_reg_set_bitmask(edt_p, OCM_CH0_CONFIG0 + base_offset, REMOTE_LOOP, (cfg->flags & EDT_OCX_REMOTE_LPBK));

    /* set LIU PRBS7 generator if requested */
    edt_reg_set_bitmask(edt_p, OCM_CH0_CONFIG0 + base_offset, PRBS_EN, (cfg->flags & EDT_OCX_PRBS_EN));


    rx_ctrl = (u_char) edt_reg_read(edt_p, OCM_RX_CTRL + mezzanine_offset);

    if (cfg->flags & EDT_OCX_FRAMED)
    {
        rx_ctrl |= FRAME_EN;
        if ((cfg->flags & EDT_OCX_DESCRAMBLE) == 0)
            rx_ctrl |= DISABLE_SCRAM;
        else
            rx_ctrl &= ~DISABLE_SCRAM;
    }
    else
        rx_ctrl &= ~FRAME_EN;

    if (cfg->flags & EDT_OCX_ENABLE_MEM)
        rx_ctrl |= RX_DATA_SRC_2G;
    else
        rx_ctrl &= ~RX_DATA_SRC_2G;

    edt_reg_write(edt_p, OCM_RX_CTRL + mezzanine_offset, rx_ctrl); 

    rx_filter = (u_char) edt_reg_read(edt_p, OCM_RX_FILTER + mezzanine_offset);
    rx_filter &= ~OVERHEAD_ONLY; 
    if (cfg->flags & EDT_OCX_OVHD_ONLY) 
    {
        if (cfg->flags & EDT_OCX_FRAMED)
            rx_filter |= OVERHEAD_ONLY; 
        else
            edt_msg(EDT_MSG_WARNING,"Overhead filter does not work in raw data mode\n");
    }
    edt_reg_write(edt_p, OCM_RX_FILTER + mezzanine_offset, rx_filter); 

    FRETURN_I("edt_ocm_channel_setup",0);
    return 0;
}

int
edt_ocm_wait_for_frame(EdtDev *edt_p, int timeout)

{
    u_int cfg;
    int mezzanine_offset = 0;
    int t = 100;
    int rc = 0;

    FENTER("edt_ocm_wait_for_frame");

    if (edt_p->channel_no == 1)
    {
        mezzanine_offset = OFFSET_CH1_MEZ;
    }

    edt_msg(EDTLIB_MSG_INFO_1,"Waiting for frame CH%d", edt_p->channel_no);

    edt_msleep(100);

    while (((cfg = edt_reg_read(edt_p, OCM_RX_STATUS + mezzanine_offset)) & FRAMED) == 0 &&
        t < timeout)
    {
        edt_msg(EDTLIB_MSG_INFO_1,".");
        cfg = edt_reg_read(edt_p, OCM_RX_CTRL + mezzanine_offset);
        edt_reg_write(edt_p, OCM_RX_CTRL + mezzanine_offset, cfg | RESET_FRM);  /* set reset frame */
        edt_reg_write(edt_p, OCM_RX_CTRL + mezzanine_offset, cfg);  /* clear it */
        edt_msleep(100);
        t += 100;
    }

    if (t < timeout)
        edt_msg(EDTLIB_MSG_INFO_1," framed\n");
    else
    {
        edt_msg(EDTLIB_MSG_FATAL," Framing timed out in %d ms\n", timeout);
        rc = -1;
    }

    FRETURN_I("edt_ocm_wait_for_frame", rc);

    return rc;

}

/***************************************
*
* OC192 board-specific functions
* Most other than the _mdio_ access functions
* have an euqivalent OCM function
*
**************************************/

/***************************************
*
* OC192 mdio functions to talk to the LIU
*
**************************************/


unsigned char 
edt_oc192_mdio_read(EdtDev *edt_p, unsigned char address)
{
    unsigned char result=0, byte;
    unsigned int val;
    int i;

    FENTER_I("edt_oc192_mdio_read",address);
    val = 0x60000000;
    val |= ((unsigned int) (address & 0x1f))<<18;
    edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_TRI);
    edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_TRI | SCLK_TRI);
    result = 0;
    for (i=31; i>=0; i--) {
        if (i>17) {
            if (!((val>>i) & 0x1)) {
                edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_TRI | SCLK_TRI);
                edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_TRI | SCLK | SCLK_TRI);
            } else {
                edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_OUT | SDATA_TRI | SCLK_TRI);
                edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_OUT | SDATA_TRI | SCLK | SCLK_TRI);
            }
            edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_TRI | SCLK_TRI);
        } else {
            edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SCLK_TRI);
            edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SCLK | SCLK_TRI);
            if (i<=8 && i>=1) {
                byte = edt_intfc_read(edt_p, OC192_LIU_MDIO_BUS) & SDATA_IN;
                result |= ((byte>>4)<<(i-1));
            }
        }
    }
    edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SCLK_TRI);
    edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SCLK | SCLK_TRI);
    edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SCLK);
    edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, 0);

    FRETURN_I("edt_oc192_mdio_read",result);
    return result;
}

void
edt_oc192_mdio_write(EdtDev *edt_p, unsigned char address, unsigned char value)
{
    unsigned int val;
    int i;

    FENTER_I_I("edt_oc192_mdio_write",address, value);
    val = 0x50020000;
    val |= ((((unsigned int) (address & 0x1f))<<18) | (unsigned int) value);
    edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_TRI);
    edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_TRI | SCLK_TRI);
    for (i=31; i>=0; i--) {
        if (!((val>>i)&0x1)) {
            edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_TRI | SCLK_TRI);
            edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_TRI | SCLK | SCLK_TRI);
        } else {
            edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_OUT | SDATA_TRI | SCLK_TRI);
            edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_OUT | SDATA_TRI | SCLK | SCLK_TRI);
        }
    }
    edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_OUT | SDATA_TRI | SCLK_TRI);
    edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_OUT | SDATA_TRI | SCLK | SCLK_TRI);
    edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_OUT | SDATA_TRI | SCLK_TRI);
    edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_OUT | SDATA_TRI | SCLK | SCLK_TRI);

    edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_OUT | SCLK) ;
    edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, 0);
    FRETURN("edt_oc192_mdio_write");
}

void 
edt_oc192_mdio_init(EdtDev *edt_p)
{
    int i;

    FENTER("edt_oc192_mdio_init");

    edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_OUT | SDATA_TRI);
    edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_OUT | SDATA_TRI | SCLK_TRI);
    for (i=32; i>=0; i--) {
        edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_OUT | SDATA_TRI | SCLK_TRI);
        edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_OUT | SDATA_TRI | SCLK | SCLK_TRI);
    }
    edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, SDATA_OUT | SCLK);
    edt_intfc_write(edt_p, OC192_LIU_MDIO_BUS, 0);
    FRETURN("edt_oc192_mdio_init");
}

void
edt_oc192_reset_liu(EdtDev *edt_p)

{
    FENTER("edt_oc192_reset_liu");
    /* Reset the AMCC S19235 */
    edt_intfc_write(edt_p, OC192_ENABLE, edt_intfc_read(edt_p, OC192_ENABLE) | AMCC_RST);
    edt_msleep(100);
    edt_intfc_write(edt_p, OC192_ENABLE, edt_intfc_read(edt_p, OC192_ENABLE) & ~AMCC_RST);
    edt_msleep(100);
    edt_oc192_mdio_init(edt_p);
    FRETURN("edt_oc192_reset_liu");
}

void
edt_oc192_mdio_set_clock(EdtDev *edt_p)

{

}

void
edt_oc192_mdio_set_swap(EdtDev *edt_p, int on)

{
    FENTER("edt_oc192_mdio_set_swap");
    edt_oc192_mdio_write(edt_p, 0x2, 
        (edt_oc192_mdio_read(edt_p, 0x2) & 0xfb) | ((on)? 0x2 : 0) );
    FRETURN("edt_oc192_mdio_set_swap");
}

void
edt_oc192_mdio_dump(EdtDev *edt_p)

{       
    uint_t i;

    for (i=1; i<=0x1f; i++)
        if (i<0x11 || i>0x1d)
            printf("%02xH       :  %02xH\n", i, edt_oc192_mdio_read(edt_p, (u_char) i));
}


void
edt_oc192_mdio_loopback(EdtDev *edt_p, int on)

{
    FENTER("edt_oc192_mdio_loopback");
    edt_oc192_mdio_write(edt_p, 0x1, edt_oc192_mdio_read(edt_p, 0x1) & 0xfd | ((on)? 0:0x2) );
    FRETURN("edt_oc192_mdio_loopback");
}

void
edt_oc192_mdio_set_prbs23(EdtDev *edt_p, int on)
{
    /*
    * Select prbs23 code
    */
    FENTER("edt_oc192_mdio_set_prbs23");
    edt_oc192_mdio_write(edt_p, 0x6, (edt_oc192_mdio_read(edt_p, 0x6) & 0xe7) | (on) ? 0x10 : 0);
    FRETURN("edt_oc192_mdio_set_prbs23");
}

void
edt_oc192_mdio_set_prbs31(EdtDev *edt_p, int on)
{
    /*
    * Select prbs23 code
    */
    FENTER("edt_oc192_mdio_set_prbs31");
    edt_oc192_mdio_write(edt_p, 0x6, (edt_oc192_mdio_read(edt_p, 0x6) & 0xe7) | (on) ? 0x11 : 0);
    FRETURN("edt_oc192_mdio_set_prbs31");
}

void
edt_oc192_mdio_standard(EdtDev *edt_p)

{
    FENTER("edt_oc192_mdio_standard");
    /*
    * Refclk is 155.52, turn on DATA_SWAP
    */
    edt_oc192_mdio_set_swap(edt_p, 1);

    /*
    * Bit 2-0
    * Phase offset between high speed recovered data and clock for improved BER
    * 000 => + 8.5 ps (default)
    * 111 => - 11.0 ps
    *
    * Bit 7-6
    * Post amplifier offset adjust
    * 
    */
    /* 
    * post amp equalization adjust
    * bit 4-2
    * 000               No equalization                         -0.8dB
    * 001               0% - 5%                                         1.4dB
    * 010               5% - 10%                                        2.4dB
    * .......
    * 111               30% - 35%                                       7.5dB
    */
    edt_oc192_mdio_write(edt_p, 0xe, (edt_oc192_mdio_read(edt_p, 0xe) & 0xfb) | 0x18 );

    FRETURN("edt_oc192_mdio_standard");
}

int
edt_oc192_set_liu(EdtDev *edt_p, int mode)

{
    int rc = 0;
    FENTER("edt_oc192_set_liu");

    edt_oc192_reset_liu(edt_p);

    switch(mode)
    {
    case EDT_OC192_LIU_NORMAL:
        edt_oc192_mdio_standard(edt_p);
        break;

    case EDT_OC192_LIU_LOOPBACK:
        edt_oc192_mdio_set_swap(edt_p, 1);
        edt_oc192_mdio_loopback(edt_p, 1);
        break;

    case EDT_OC192_LIU_BIST_TX:
        /*
        * Refclk is 155.52, turn on DATA_SWAP
        */
        edt_oc192_mdio_set_swap(edt_p, 1);
        /*
        * Select prbs23 code
        */
        edt_oc192_mdio_write(edt_p, 0x6, (edt_oc192_mdio_read(edt_p, 0x6) & 0xf7) | 0x10);
        /*
        * Transmit built in self test mode
        */
        edt_oc192_mdio_write(edt_p, 0x5, edt_oc192_mdio_read(edt_p, 0x5) | 0x40);
        /*
        * Turn on diagnostic loopback
        */
        edt_oc192_mdio_loopback(edt_p, 1);
        break;

    case EDT_OC192_LIU_BIST_TX_EXT:
        /*
        * Refclk is 155.52, turn on DATA_SWAP
        */
        edt_oc192_mdio_set_swap(edt_p, 1);
        /*
        * Select prbs23 code
        */
        edt_oc192_mdio_write(edt_p, 0x6, (edt_oc192_mdio_read(edt_p, 0x6) & 0xf7) | 0x10);
        /*
        * Transmit built in self test mode
        */
        edt_oc192_mdio_write(edt_p, 0x5, edt_oc192_mdio_read(edt_p, 0x5) | 0x40);
        /*
        * Turn off diagnostic loopback
        */
        edt_oc192_mdio_loopback(edt_p, 0);
        break;

    case EDT_OC192_LIU_BIST_RX:
        /*
        * Refclk is 155.52, turn on DATA_SWAP
        */
        edt_oc192_mdio_set_swap(edt_p, 1);
        /*
        * Select prbs23 code
        */
        edt_oc192_mdio_write(edt_p, 0x6, (edt_oc192_mdio_read(edt_p, 0x6) & 0xf7) | 0x10);
        /*
        * Receive built in self test mode
        * turn on line loopback
        */
        edt_oc192_mdio_write(edt_p, 0x5, edt_oc192_mdio_read(edt_p, 0x5) | 0x04);
        break;

    default:
        rc = -1;
    }

    FRETURN_I("edt_oc192_set_liu",rc);
    return rc;
}



int
edt_oc192_lock_clocks(EdtDev *edt_p, int timeout)

{


    if (edt_ocx_lock_local_clock(edt_p, timeout) ||
        edt_ocx_lock_channel_clock(edt_p, edt_p->channel_no, timeout))

        return -1;

    edt_msg(EDTLIB_MSG_INFO_1,"All System clocks locked          \n");

    return 0;

}

int
edt_msdv_lock_clocks(EdtDev *edt_p, int timeout)

{


    if (edt_ocx_lock_local_clock(edt_p, timeout) ||
            (edt_wait_register_bits_high (edt_p, OCM_CH0_ENABLE, SYS_LOCK,timeout)))
    {
        edt_msg(EDTLIB_MSG_FATAL,"\rMezzanine System clock not locked");
        return -1;

    }

    edt_msg(EDTLIB_MSG_INFO_1,"All System clocks locked          \n");

    return 0;

}

char *
edt_oc192_mezz_filename(EdtDev *edt_p, EdtLineRate line_rate)

{
    char *target_bitfile = NULL;

    switch (line_rate) {
        case OC3_RATE:      
        case OC12_RATE:     
        case STM1_RATE:
        case STM4_RATE:
            if (edt_p->mezz.extended_rev == 2)
                target_bitfile="oc12m2.bit";
            else
                target_bitfile="oc12m.bit";


            break;

        case STM16_RATE:            
        case OC48_RATE:     
            if (edt_p->mezz.extended_rev == 2)
                target_bitfile="oc48m2.bit";
            else
                target_bitfile="oc48m.bit";

            break;

        case STM64_RATE:
        case OC192_RATE:
            if (edt_p->mezz.extended_rev == 2)
                target_bitfile="oc192m2.bit";
            else
                target_bitfile="oc192m.bit";
            break;

    }

    return target_bitfile;

}


char *
edt_net10g_mezz_filename(EdtDev *edt_p, EdtLineRate line_rate)

{
    char *target_bitfile = NULL;

    target_bitfile = "net10g_v5_sdh.bit";



    return target_bitfile;

}



int
edt_oc192_load_default_mezzanine(EdtDev *edt_p, EdtLineRate line_rate,
                                 char *mezz_0, char *mezz_1)

{
    int rc = 0;

    char *bitname = edt_oc192_mezz_filename(edt_p, 
        (line_rate)?line_rate:OC192_RATE);

    if (mezz_0)
        if (mezz_0[0])
            bitname = mezz_0;

    rc = edt_bitload(edt_p, ".", bitname, BITLOAD_FLAGS_MEZZANINE, 0);

    return rc;
}


int
edt_oc192_speed_capable(EdtDev *edt_p, EdtLineRate line_rate)

{
    int rc = -1;

    switch (line_rate) {
        case STM1_RATE:
        case STM4_RATE:
        case STM16_RATE:            
        case OC3_RATE:      
        case OC12_RATE:     
        case OC48_RATE:     
            if ((edt_p->channel_no & 1) == 0)
                rc = 0;
            break;

        case STM64_RATE:
        case OC192_RATE:
            if ((edt_p->channel_no & 1) == 1)
                rc = 0;
            break;

        case GIGE_RATE:
            rc =  -1;
            break;

        default:
            edt_msg(EDTLIB_MSG_FATAL,"Unknown bit rate %d\n", line_rate);
            rc =  -1;

    } 
    return rc;

}





int
edt_oc192_has_mezz_bitfile(EdtDev *edt_p, char *bitfile_name)

{
    int rc;
    FENTER_S("edt_oc192_has_correct_bitfile",bitfile_name);

    rc = strncmp(edt_p->bfd.mezz_name0, bitfile_name, strlen(bitfile_name));

    FRETURN_I("edt_oc192_has_correct_bitfile",rc);

    return rc;
}

int
edt_net10g_has_mezz_bitfile(EdtDev *edt_p, char *bitfile_name)

{
    int rc;
    FENTER_S("edt_net10g_has_correct_bitfile",bitfile_name);

    rc = strncmp(edt_p->bfd.mezz_name0, bitfile_name, strlen(bitfile_name));

    FRETURN_I("edt_net10g_has_correct_bitfile",rc);

    return rc;
}

int
edt_oc192_set_clock_select(EdtDev *edt_p, EdtLineRate line_rate)

{
    int channel = edt_p->channel_no;


    FENTER_I("edt_oc192et_clock_select", line_rate);

    if (channel == 0) 
    {
        edt_reg_write(edt_p, OC192_CHAN_SELECT, 0x0);

        return edt_ocm_set_clock_select(edt_p, line_rate);

    }
    else
    {
        edt_reg_write(edt_p, OC192_CHAN_SELECT, 0x1);
        /* somehow affecting module not ready */
        edt_reg_write(edt_p, OC192_ENABLE, PLL_EN);

        edt_msleep(1000);

        /* seelect clock in register FIX !!!*/

    }

    FRETURN("edt_ocx_set_clock_select");

    return 0;

}

int
edt_oc192_clear_demux(EdtDev *edt_p)

{
    int i;

    FENTER("edt_oc192_clear_demux");

    /* make sure demux is turned off */
    edt_reg_write(edt_p, OC192_DEMUX_BITMASK, 0);
    for (i=0x80;i<0x8c;i++)
        edt_reg_write(edt_p, OC192_DEMUX_MASK_ADDR, i);


    FRETURN("edt_oc192_clear_demux");

    return 0;

}

void
edt_oc192_set_framer(EdtDev *edt_p, int flags)

{

    int rx_ctrl;

    FENTER_I("edt_oc192_set_framer", flags);

    rx_ctrl = 0;
    if (flags & EDT_OCX_FRAMED)
    {
        rx_ctrl |= OC192_FRAME_EN;
        if ((flags & EDT_OCX_DESCRAMBLE) == 0)
            rx_ctrl |= OC192_DISABLE_SCRAM;
    }

    edt_reg_write(edt_p, OC192_FRAMING, rx_ctrl);

    FRETURN("edt_oc192_set_framer");

}

int
edt_oc192_channel_lock_frontend(EdtDev *edt_p, EdtOCConfig *cfg)

{
    int rc;
    int rx_filter;

    /* AMCC received clock not locked */

    if ((rc = edt_wait_register_bits_high(edt_p, OC192_LIU_STATUS, 0x1, cfg->timeout)))
    {
        edt_msg(EDTLIB_MSG_FATAL,"AMCC receiver won't lock\n");
        return -1;
    }
    else
        edt_msg(EDTLIB_MSG_INFO_1,"AMCC receiver PLL is locked\n");

    /* added 2/13/2008 jsc */

    rx_filter = (u_char) edt_reg_read(edt_p, OC192_RCV_FILTER);
    rx_filter &= ~OVERHEAD_ONLY; 
    if (cfg->flags & EDT_OCX_OVHD_ONLY) 
    {
        if (cfg->flags & EDT_OCX_FRAMED)
            rx_filter |= OVERHEAD_ONLY; 
        else
            edt_msg(EDT_MSG_WARNING,"Overhead filter does not work in raw data mode\n");
    }
    edt_reg_write(edt_p, OC192_RCV_FILTER, rx_filter); 

    edt_reg_write(edt_p, OC192_ENABLE, 0);
    edt_reg_write(edt_p, OC192_ENABLE, 0x2);
    edt_reg_write(edt_p, OC192_ENABLE, 0x6);
    edt_reg_write(edt_p, OC192_ENABLE, 0xe);
    edt_reg_write(edt_p, OC192_ENABLE, 0x1e);
    edt_msleep(100);

    /* Received DCM not locked */
    if ((rc = edt_wait_register_bits_high(edt_p, OC192_ENABLE, 0xb0, cfg->timeout)))
    {
        edt_msg(EDTLIB_MSG_FATAL,"Receive DCM won't lock\n");
        return -1;

    }
    else
        edt_msg(EDTLIB_MSG_INFO_1,"Receive DCM Locked\n");



    return 0;

}

int
edt_net10g_channel_lock_frontend(EdtDev *edt_p, EdtOCConfig *cfg)

{
    int rc;
    int rx_filter;

    /* AMCC received clock not locked */

    if ((rc = edt_wait_register_bits_high(edt_p, OC192_LIU_STATUS, 0x1, cfg->timeout)))
    {
        edt_msg(EDTLIB_MSG_FATAL,"AMCC receiver won't lock\n");
        return -1;
    }
    else
        edt_msg(EDTLIB_MSG_INFO_1,"AMCC receiver PLL is locked\n");

    /* added 2/13/2008 jsc */

    rx_filter = (u_char) edt_reg_read(edt_p, OC192_RCV_FILTER);
    rx_filter &= ~OVERHEAD_ONLY; 
    if (cfg->flags & EDT_OCX_OVHD_ONLY) 
    {
        if (cfg->flags & EDT_OCX_FRAMED)
            rx_filter |= OVERHEAD_ONLY; 
        else
            edt_msg(EDT_MSG_WARNING,"Overhead filter does not work in raw data mode\n");
    }
    edt_reg_write(edt_p, OC192_RCV_FILTER, rx_filter); 

    edt_reg_write(edt_p, OC192_ENABLE, 0);
    edt_reg_write(edt_p, OC192_ENABLE, 0x2);
    edt_reg_write(edt_p, OC192_ENABLE, 0x6);
    edt_reg_write(edt_p, OC192_ENABLE, 0xe);
    edt_reg_write(edt_p, OC192_ENABLE, 0x1e);
    edt_msleep(100);

    /* Received DCM not locked */
    if ((rc = edt_wait_register_bits_high(edt_p, OC192_ENABLE, 0xb0, cfg->timeout)))
    {
        edt_msg(EDTLIB_MSG_FATAL,"Receive DCM won't lock\n");
        return -1;

    }
    else
        edt_msg(EDTLIB_MSG_INFO_1,"Receive DCM Locked\n");



    return 0;

}


int
edt_oc192_channel_setup(EdtDev *edt_p, 
                        EdtOCConfig *cfg)

{
    int rc;

    edt_reg_write(edt_p, OC192_CHAN_SELECT, 0x1);

    /* turn off output as prbs (must be turned off for tagging) */

    edt_reg_write(edt_p, OC192_OUTPUT_DATA_SEL, 0);
    /* power up transceiver */

    edt_reg_write(edt_p, OC192_XCVR_CTL_STAT, 0x4);

    if (rc = edt_wait_register_bits_low(edt_p, OC192_XCVR_CTL_STAT, 0x50, cfg->timeout))
    {
        edt_msg(EDTLIB_MSG_FATAL,"module absent/loss of signal/(module not ready)\n");
        return -1;
    }

    if(cfg->flags & EDT_OCX_LOOPBACK) {
        edt_oc192_set_liu(edt_p, EDT_OC192_LIU_LOOPBACK);
        edt_reg_write(edt_p, OC192_OUTPUT_DATA_SEL, 0x19);
    } else {
        edt_oc192_set_liu(edt_p, EDT_OC192_LIU_NORMAL);
    }

    /* set framer */

    edt_oc192_set_framer(edt_p, cfg->flags);

    if (cfg->flags & EDT_OCX_TAGGED_DATA)
        edt_oc192_set_tagging(edt_p,1,cfg->tagid);

    return 0;
}

int
edt_net10g_channel_setup(EdtDev *edt_p, 
                        EdtOCConfig *cfg)

{
    int rc;

    edt_reg_write(edt_p, OC192_CHAN_SELECT, 0x1);

    /* turn off output as prbs (must be turned off for tagging) */

    edt_reg_write(edt_p, OC192_OUTPUT_DATA_SEL, 0);
    /* power up transceiver */

    edt_reg_write(edt_p, OC192_XCVR_CTL_STAT, 0x4);

    if (rc = edt_wait_register_bits_low(edt_p, OC192_XCVR_CTL_STAT, 0x50, cfg->timeout))
    {
        edt_msg(EDTLIB_MSG_FATAL,"module absent/loss of signal/(module not ready)\n");
        return -1;
    }

    if(cfg->flags & EDT_OCX_LOOPBACK) {
        edt_oc192_set_liu(edt_p, EDT_OC192_LIU_LOOPBACK);
        edt_reg_write(edt_p, OC192_OUTPUT_DATA_SEL, 0x19);
    } else {
        edt_oc192_set_liu(edt_p, EDT_OC192_LIU_NORMAL);
    }

    /* set framer */

    edt_oc192_set_framer(edt_p, cfg->flags);

    if (cfg->flags & EDT_OCX_TAGGED_DATA)
        edt_oc192_set_tagging(edt_p,1,cfg->tagid);

    return 0;
}

int
edt_oc192_wait_for_frame(EdtDev *edt_p, int timeout)

{
    int rc = 0;

    FENTER("edt_oc192_wait_for_frame");

    edt_msg(EDTLIB_MSG_INFO_1,"Waiting for frame CH%d", edt_p->channel_no);

    if (rc = edt_wait_register_bits_high(edt_p, OC192_FRAMING, 
        OC192_FRAME_LOCK , timeout))
    { 
        edt_msg(EDTLIB_MSG_FATAL," - Framing timed out\n");
        rc = -1;
    }
    else
        edt_msg(EDTLIB_MSG_INFO_1," framed\n");

    FRETURN_I("edt_oc192_wait_for_frame", rc);

    return rc;

}

int
edt_oc192_set_tagging(EdtDev *edt_p, int state, int tagid)

{
    u_char mask = 0;

    if (state)
    {
        /* All boards are set up to acquire only selected