lib_srxl.h

#ifndef LIB_SRXL_H_
#define LIB_SRXL_H_

#include "edtinc.h"

/* ***************** SRXL related registers *****************/
/* SRXL Spartan3 registers.
   They're on the srxl mezzanine board xilinx,
   but accessed through the gs/ss user interface xilinx w/ 
   the srxl bitfile loaded.
 */
#define SRXL_DDS_CTRL (INTFC_BYTE | 0x50)
#define SRXL_DDS_DATA (INTFC_BYTE | 0x51)
#define SRXL_SERIAL_CTRL (INTFC_BYTE | 0x54)
#define SRXL_DACA_LOW (INTFC_BYTE | 0x58)
#define SRXL_DACB_LOW (INTFC_BYTE | 0x5a)
#define SRXL_PLL_LOW (INTFC_BYTE | 0x5c)
#define SRXL_CLK_CTRL (INTFC_BYTE | 0x5f)
#define SRXL_AD_READ_DATA (INTFC_BYTE | 0x60) 
#define SRXL_AD_CAPTURE_CTRL (INTFC_BYTE | 0x63)
#define SRXL_GC_ADDR (INTFC_BYTE | 0x64)
#define SRXL_GC_DATA (INTFC_BYTE | 0x65)


/* Interface xilinx registers used during programming of SRXL 
 * mezz-board xilinx. These registers are very similar to the 
 * OCM's registers, so see edt_ocm.h for more documentation. 
 */
#define SRXL_X_DATA (INTFC_BYTE | 0x40)
#define SRXL_X_CTRL (INTFC_BYTE | 0x41)
#define SRXL_X_STAT (INTFC_BYTE | 0x42)

/* SRXL_X_CTRL bits: control (programming) register bits */
#define SRXL_X_CTRL_INIT 0x01     /* tristates init pin, starts init and enables readback */
#define SRXL_X_CTRL_PROG 0x02     /* starts/resets xilinx program */
#define SRXL_X_CTRL_PROG_EN 0x20  /* enables xilinx programming */
#define SRXL_X_CTRL_FIFO_EN 0x40  /* enables fifo */

/* SRXL_X_STAT bits: status register bits.
 * The top 4 bits of the status register are the number of bytes in the fifo,
 *  SRXL_X_STAT_FIFO_CNT(edt_p) will give that number.  
 */
#define SRXL_X_STAT_INIT 0x01
#define SRXL_X_STAT_DONE 0x02
#define SRXL_X_STAT_FCNT_MSK            0xf0 /* mask to give just the fifo count */
#define SRXL_X_STAT_FCNT_SHFT           4    /* amount to right shift to get fifo count */
#define SRXL_X_STAT_FIFO_CNT(dev) ((edt_reg_read((dev), SRXL_X_STAT)>>SRXL_X_STAT_FCNT_SHFT) & SRXL_X_STAT_FCNT_MSK) 

/* SERIAL_CTRL register bits */
#define SRXL_SERIAL_CTRL_XFER_BUSY 0x80

#define SRXL_X_CONST 0x43
#define SRXL_CONSTANT 0x0c    /* fixed pattern in SRXL_X_CONST register */

/* Note the SRXL user intfc. xilinx also provides: */
 /* VHDL NAME     ADDR   edtreg.h 
    -----------------------------
    CMD_REG       0x00   PCD_CMD
    DATA_PATH_REG 0x01  
    FUNCT_REG     0x02   
        BD_ID_REG     0x7f   MEZZANINE_BD_ID
    CONFIG_REG    0x0F
    CH_EN_REG     0x10   SSD16_CHENL
    LSB_FIRST_REG 0X16   SSD16_LSB
 */
/* **************** end SRXL registers ***********************/


EDTAPI void srxl_serial_write(EdtDev *edt_p, uint_t desc, uint_t val);
EDTAPI void srxl_gc_write(EdtDev *edt_p, int chip, uint_t address, uint_t value);
EDTAPI void srxl_gc_set_page(EdtDev *edt_p, int chip, int page);
EDTAPI int srxl_set_sample_clk(EdtDev* edt_p, float samp_freq);
EDTAPI int srxl_set_if_losc(EdtDev *edt_p, unsigned freq);
EDTAPI int srxl_set_lb_losc(EdtDev *edt_p, unsigned freq);
 /* end group srxl */

#endif 

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