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ECL Mezzanine

Data sheet / Specifications

Drivers and Software
Documentation

General Purpose ECL Mezzanine Board

Features

• 32 ECL input/output signals
• Transfer rates up to 60 megabits per seconds per signal
• Provides 16 high-speed DMA channels between ECL devices and a PCI Local Bus computer
• Large Xilinx FPGA
• Two large synchronous static memory banks (PCI SS) or one memory bank up to 1 GB (PCI GS)
• LVDS external clock that can be used to synchronize the output data
• Single short PCI Local Bus slot
• Fast transfers using a 66 MHz 32-bit PCI or 8-Lane PCI Express
• Configuration files for 16 synchronous serial channels
• Optional: two T1/E1 input/output channels
• Optional: SSE two simultaneous input channels and one output channel (400 Megabit per second synchronous serial ECL)

Applications

• Telemetry receiver and transmitter
• Monitoring serial data communications
• Satellite ground station support

Description

The ECL is a mezzanine board for the PCI SS, PCI GS, or PCIe8 LX main board, and provides 32 differential ECL interface signals. The ECL signals can be inputs or outputs in groups of four (two channels). The function of each signal is determined by the FPGA configuration file used on the main board.

The ECL mezzanine board is supplied with FPGA configuration files that implement 16 synchronous serial channels. Each channel inputs or outputs a data signal on the edge of the associated clock. The data is stored in or sent from host memory using the PCI DMA. This configuration provides a simple, flexible solution for telemetry, satellite, and monitoring applications.

A large Xilinx Virtex™-E (PCI SS) or Virtex™-II Pro (PCI GS) FPGA and associated memory allows the user to implement an FPGA configuration and process large amounts of serial ECL data. The separate high-speed 16-channel PCI DMA controller allows flexible access to host memory.