The SSEP is a mezzanine board for the PCI SS, PCI GS, or PCIe8 LX
main board, and samples the data on the rising edge of the clock and stores it in host memory by the main board DMA.
One 15-pin D connector is provided. Each channel accepts a differential data signal (two wires) and a differential clock (two more wires) at standard ECL signal levels. The output channel has one differential data signal and one differential clock. All input signals are terminated through 50 ohms to -2 volts.
The SSE has an additional differential data signal that can be used in applications where notification of a start or an end of a block transfer is necessary.
The SSEP has a programmable oscillator on-board. The legacy SSE comes without the programmable oscillator. For legacy applications where the SSE was used, specify no P (no oscillator).