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SSEP / SSE Mezzanine

Data sheet / Specifications

Drivers and Software
Documentation

400 megabit per second synchronous serial interface

Features

  • Transfer rates up to 400 megabits per second per channel
  • Three channels (two input or one input, one output)
  • One data bit per channel
  • ECL-compatible driver/receivers
  • Implements a high-speed DMA channel between an external device and PCI or PCI Express bus computer
  • Customizable FPGA
  • Reed-Solomon encoding/decoding [more]
  • Optional: 32 ECL/RS422/LVDS signals

Applications

  • Telemetry receiver
  • Monitoring serial data communications
  • Satellite ground station support

Description

The SSEP is a mezzanine board for the PCI SS, PCI GS, or PCIe8 LX main board, and samples the data on the rising edge of the clock and stores it in host memory by the main board DMA.

One 15-pin D connector is provided. Each channel accepts a differential data signal (two wires) and a differential clock (two more wires) at standard ECL signal levels. The output channel has one differential data signal and one differential clock. All input signals are terminated through 50 ohms to -2 volts.

The SSE has an additional differential data signal that can be used in applications where notification of a start or an end of a block transfer is necessary.

The SSEP has a programmable oscillator on-board. The legacy SSE comes without the programmable oscillator. For legacy applications where the SSE was used, specify no P (no oscillator).

Ordering

When ordering, specify which main board (PCI SS, PCI GS or PCIe8 LX). For other options, see the data sheet [pdf].

 

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Engineering Design Team
1100 NW Compton Dr, Suite 306
Beaverton, OR 97006